Presetter for timers

ABSTRACT

A PRESET TIMER SYSTEM INCLUDING A TIMER WHICH NORMALLY COUNTS AT A REAL TIME RATE AND PROVIDES AN ACTUATION UPON REACHING A FULL COUNT, AND AN ASSOCIATED PRESETTER WHICH SUPPLIES PULSES TO THE TIMER AT A COMPRESSED NON-REAL TIME RATE. SWITCHES ARE SELECTIVELY SET BY THE OPERATOR TO INDICATE THE DESIRED TIMER INTERVAL, AND THESE SWITCHES ARE SO CONNECTED TO ELECTRONIC DECIMAL COUNTERS THAT, WHEN THE TIMER IS PRESET, A NUMBER OF PULSES IS SUP-   LIED TO THE TIMER WHICH IS THE COMPLEMENT OF THE DESIRED TIMER INTERVAL.

Feb. 16,1971

`F'led Jan. 22, 1.969

w. c. ANDERSON ETAI- PRESETTERFOR TIMERS 5 Sheets-Sheet 1 ATTO R N EYS WQ C. ANDERSCN ETAL Feb. 16, 1971 PRESETTER FCR TIMERS Filed Jan. 22., 1969 5 Sheets-Sheet 2 om@ @Emu NEV Feb. 16,1971 w, C, ANDERSQN mL 3,564,425

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Feb. 16, 1971 PRESETTER FOR TIMERS SSheets-Sheet 5 Filed Jan. 22",v 1969 T m w w 7 PW M c INVENTQRS NM M@ C.' HAIDERIOA/ P/mvn CWI/66 ATTORNEYS United States Patent Oflce 3,564,426 PRESETTER FOR TIMERS Wilmer C. Anderson, Greenwich, and Richard Cruger,

Stamford, Conn., assignors to General Time Corporation, Stamford, Conn.

Filed Jan. 22, 1969, Ser. No. 793,003 Int. Cl. H03k 21/32 U.S. Cl. 328-48 12 Claims ABSTRACT OF THE DISCLOSURE This invention relates to a preset timer system -and more specically to a system wherein the complement of a preselected number of pulses is supplied to a timer before the interval timing operation is started.

An interval timer can be a device which is provided with pulses at a predetermined repetition rate, as from a clock pulse source, and which then performs a control function, deactivates itself, or provides an alarm signal when ithas reached a full count. The timer -rnay be designed to have a predetermined maximum count such as, for example, 1,000 hours or 10,000 hours. In many cases, especially when the timer is to be used at some relatively inaccessible location, it is impossible for an operator to read the timer or to retrieve it periodically for reading for the purpose of determining when a desired time interval has elapsed.

For this purpose, presetters are used, the general purpose of the presetter being to supply to the timer a number of pulses in compressed non-real time so that, when the timing interval is commenced, the timer will already have a count of known magnitude stored therein and it need only count the remaining span to its maximum in order to define the desired interval. For example, using a counter having a 1,000 hour maximum, `and assuming that during the timing interval clock pulses would be provided at the rate of one per hour, and further assuming that it is desirable to measure an interval of 547 hours, the presetter would be used to insert a count equivalent to LOCO-547:45?, hours. These pulses should be supplied to the counter in a very short period of time, on the order of a few seconds, so that the presetting operation can be done with minimum loss of time. Also, the presetter should be of high reliability, good accuracy and minimum complexity and cost.

An object of the present invention is to provide a preset timer system which is relatively simple to manufacture and for which the cost is minimized.

A further object is to provide apparatus which can be constructed using presently available integrated circuit logic elements and with printed circuit assembly techniques to minimize size, weight and manufacturing complexities.

Yet another object is to provide apparatus which is reliable, which can be set with no preliminary calculation, and which performs the presetting operation in a very short time.

In order that the manner in which the foregoing and other objects are attained in accordance with the inven- 3,564,426 Patented Feb. 16, 1971 tion can be understood in detail, particularly advantageous embodiments thereof will be described with reference to the accompanying drawings, which form a part of this specification, and wherein:

FIG. 1 is a perspective View illustrating the presetter coupled to a timer unit;

FIG. 2A is a block diagram of the presetter circuit;

FIG. 2B is a block diagram of the associated timer circuit;

FIG. 3 is a schematic diagram of one embodiment of the presetting apparatus;

FIG. 4 is a detailed schematic diagram of portions of the apparatus of FIG. 3;

FIG. 5 is a truth table usable in discussing the apparatus of FIG. 4;

FIG. 6 is a count-complementary count table useful in explaining the apparatus of FIG. 4;

FIG. 7 is a schematic diagram of a further embodiment of a presetting apparatus in accordance with the present invention;

FIG. 8 is a schematic diagram of a pulse source for use in the presetter;

FIG. 9 is a schematic daigram of an indicator circuit for use in the presetter.

The presetter can be housed in a unit 1 connectable to a timer unit 3 by means of la cable 2. The presetter includes selector switch circuitry 4 including the switch knobs upon which the operator sets in the desired time interval. Thus, if the timer is a 1,000 hour timer and the operator desires an actuation after 547 hours, he sets the knobs to a position showing 5-4-7 on the indicia associated with the knobs. The operator next moves a switch 5 from the off position to the reset position and then depresses a reset push button 8 to reset the counting circuits in both the presetter and the timer. At this time the operator should observe the meter 6 to ensure that sufficient battery potential is available for proper operation. Next, switch 5 is moved to a preset position. This causes the presetter to supply a number of pulses to timer unit 3 which is the complement of the number appearing on selector switches 4. Thus, if the knobs of the selector switches indicate the number 547, the presetter will supply 1,000-547=453 pulses to the timer. When the reset and preset operations are properly completed, an illuminated indication is provided by an indicator 7.

As shown in FIG. 2A, switch 5 is a two-pole, threeposition switch including movable contacts 5a and 5b. Pushbutton switch `3 is a two-pole, normally open, momentary contact switch including movable contacts 8a and 8b. Movable contact 5b is utilized to provide energization to the timer unit during the reset and preset operations. Accordingly, the negative terminal of a battery Sc is connected to a terminal designated GND and the positive terminal of the battery is connectable to a terminal designated +12 via movable contact 5b when switch 5 is in the reset or preset positions. The positive terminal of battery Sc is also connectable to the terminal designated reset via movable Contact 5a when switch 5 is in the reset" position and via contacts 8a when push-button switch 8 is depressed. The positive signal on the Reset terminal resets the various counting circuits in the timer unit as will be described hereinafter in more detail. When the push-button switch is actuated a positive potential is also supplied via movable contacts 8b to reset electronic counter circuit 9 and to condition indicator circuit 7.

When switch 5 is placed in the preset position, a positive potential is supplied from battery 5c to actuate turnon circuit 11a which, in turn, activates pulse source 10. Pulse source 10 provides pulses at a fixed repetition rate, these being the pulses for presetting the timer unit which occur at the compressed non-real time rate. The output of pulse source 10 is connected to a terminal designated Preset The output of the pulse source is also coupled to counter circuits 9 which, in turn, are interconnected with selector switch circuits 4. The selector switch circuits detect when the proper number of pulses have been supplied by pulse source 10, and then turn off the pulse source via turn-ott circuit 11b.

As previously mentioned, a signal is supplied via contacts 8b to condition indicator circuit 7 if switch 5 is in the reset position and push-button switch 8 is momentarily depressed. If a signal is thereafter received from selector switch circuits 4, the indicator provides the illuminated indication for the operator which informs the operator that timer unit 3 has been properly reset and preset. If either the operator fails to reset the timer unit prior to attempting to preset it, or if the preset operation is not completed, these conditions will be made known to the operator because of an absence of illumination by indicator 7.

The timer unit 3 is shown in block diagram form in FIG. 2B. The timer includes terminal connections designated reset, preset, 12 and GND, these terminations corresponding to those at the output of the presetter as shown in FIG. 2A, the interconnection being completed by cable 2 during the presetting operation.

The timer unit includes a tuning fork oscillator a which supplies pulses to a frequency divider b. The frequency divider is designed in accordance with the tuning fork oscillator frequency so that it provides one pulse per hour at its output. The output of frequency divider IJ is coupled to a counter d which counts to 1,000, this connection being via an OR circuit c. Counter d is coupled to an actuation circuit e which provides a suitable actuation such as closing a set of contacts whenever counter d reaches a full count. Where longer timer intervals are desired a counter d with a 10,000 count capacity can be used.

The Reset terminal is connected to the reset inputs of frequency divider b and counter d to reset both of these circuits to a zero or initial condition prior to presetting. The Preset terminal is coupled to the input of counter d via OR circuit c. The +12 and GND terminals are connected to each of the circuits a to e to energize the same during the preset and reset intervals.

When the timer unit as shown in FIG. 2B is coupled to the presetter as shown in FIG. 2A, the timer unit is rst reset by placing switch 5 in the reset position and by then actuating push button switch 8. Accordingly, a positive signal as supplied to the reset terminals of frequency divider b and counter d via their respective reset inputs. Thereafter, the timing unit is present by placing switch 5 in the present position. This automatically turns on pulse source which supplies a predetermined number of pulses to the timer unit corresponding to the complement of the number set on switches 4, this being done at a compressed non-real time rate. After the appropriate number of pulses have been supplied to the timer, pulse source 10 is turned off and indicator 7 provides an indication that the reset and preset operations have been completed.

When the presetting operation is completed, cable 2 is removed from timer unit 3 and the timer unit is then connected to the unit which it is to control. Energization is supplied via the +12 and GND terminals. Tuning fork oscillator a continues to operate and frequency divider b provides one pulse per hour to counter d, these pulses being at the real time rate. If the unit has been preset by insertion of 453 pulses, then after 547 hours actuation circuit e will become energized.

Referring now to FIG. 3, it will be seen that the apparatus includes a pulse source 10 the output of which is connected to one of the two input terminals of an AND gate 11, this arrangement involving AND gate 11 being an alternative for turn-on and turn-off circuits 11a and 11b in FIG. 2A. The output of gate 11 is connectable to the timer and to the counters within the presetter. The other input lo gate l1 is connected to the output of a bistable circuit 12. The positive source of voltage is connected to a terminal 13 and, through a normally open switch (such as contacts 5a in FIG. 2A) indicated generally at 14 in FIG. 3, to one input of bistable circuit 12. When switch 14 is closed, the positive voltage is connected to the bistable circuit to turn the circuit on and to provide a signal to gate 11, allowing that gate to supply pulses from the pulse source to the timer.

The output of gate 11 is connected to the input of a four-stage binary counter 15. Binary counter 15 is a conventional device having four stages and producing counts of l, 2, 4 and 8 inthe usual binary notation. Devices of the nature of counter 15 can be readily obtained at the present time in integrated circuit form suitable for mounting on a conventional printed circuit board, this being an advantageous form for the apparatus.

The l, 2, 4 and 8 outputs from counter 15 are supplied to a logic unit 16 which can be regarded as a binary to decimal converter and which provides eight of the necessary nine counts to the xed contacts of a ten position selector switch indicated generally at 17. Switch 17 can be of the type which uses printed circuit contacts for the xed contact portions of the switch. The movable contact or wiper unit can then be installed on the printed circuit, forming the completed switch.

Outputs I, 2 and 4 from counter 15 are connected to three of the inputs to a three-stage, three-input AND circuit integrated circuit strip 18. Strip 18 is an integrated circuit unit of a generally available type in which three input AND gates are constructed in a single monolith. The three outputs from counter 15 are connected to the three inputs of one of the AND gates, providing the remaining ninth count not available from converter 16. The output is connected via a conductor 19 to the sef lector switch 17 A carry and reset output is also provided by converter 16 on conductor 20, the signal on that conductor being provided to counter 15 as a reset signal and to the next counter as a rst input pulse.

From the discussion thus far, it will be apparent that counter 15, converter 16 and one of the AND circuits of AND gate strip 18 constitute a decimal counter assembly in which pulses applied to the input of counter 15 are counted in binary form and converted to decimal form, the decimal indications being connected to selector switch 17. As will appear from a discussion of FIG. 4, the outputs from converter 16 and strip 18 to the selector switch can either be the direct decimal equivalent counts from counter 15, or they can be the complementary counts. As discussed above, it is the complementary counts which are connected to the selector switch. Movement of the wiper of switch 17 to a specic one of the fixed contacts selects one of the complement counts. The wiper of switch 17 is then connected to one input of a four-input AND gate 21 which provides an output signal to deactivate the gate, as will be discussed in greater detail. The apparatus including counter 15 and the associated logic circuitry will be referred to as the units counter.

The next stage of the counter becomes active when a reset and carry signal is provided on conductor 20. This signal is connected to the one stage of a binary counter strip 22 which is similar in nature to counter 15. The l, 2 and 4 outputs from counter 22 are connected to a second three-input AND gate in gate strip 18, the count output being taken on conductor 23 to a selector switch indicated generally at 24. The l, 2, 4 and 8 outputs from counter 22 are connected to a converter 25 which is similar in nature to converter 16. Counter 25 provides eight of the necessary nine decimal indications to selector switch 24 and also provides a reset and carry signal on a conductor 26 to reset counter 22 and to provide a rst count for the successive counter, counter 30. It will be recognized that counter 22, converter 25 and the associated conductors and circuits constitute the tens counter portion of the system.

The hundreds counter portion of the system includes a counter 30, a converter 31, a selector switch 32 and the third one of the three input AND gates in strip 18, the output from that AND gate being taken on a conductor 33 to selector switch 32. The components of the hundreds portion of the counter apparatus are substantially similar to those in the units and tens portions, the carry and reset signal from converter 31 being taken on a conductor 34 to reset counter 30 and to provide a rst count input for the thousands section which includes a counter 35. If the presetter in FIG. 3 is used for a 1,000 hour counter, counters 15, 22 and 30 and associated circuitry which are capable of counting to 999 would be suicient. However, if the presetter is to be used with a 10,000 hour counter another decimal counter portion must be added as shown. This additional portion includes binary counter 35, counter 36, selector switch 37 which are the same as in the other counter portions. The l, 2 and 4 outputs from counter 35 are connected to a three-input AND gate 39 which in turn is coupled to switch 37. Counter 36 lprovides the reset signal for counter 35 via conductor 38.

The movable contacts of each of selector switches 17, 23, 32 and 37 are connected to the inputs of AND gate 21. When signals are present on all of these movable contacts, an output signal is provided on conductor 40 from AND gate 21, this signal being connected to the reset portion of the bistable circuit 12, returning that circuit to its oi condition, removing the input to AND gate 11 and terminating the flow of pulses from pulse source 10 to the timer and to counter 15. When the signal on conductor 40 appears, the presetting operation has been completed.

FIG. 4 shows a more detailed schematic diagram of one stage of the counting apparatus of FIG. 3. The stage selected for this discussion is the tens stage of the system of FIG. 3. However, it will be understood that the hundreds and thousands stages can be substantially identical, and with one exception to be discussed later the units stage is also identical. The input pulses for the stage are provided on conductor -41 to the input of counter 22. The outputs of stages 1, 2, and 4 of counter 22 are connected to AND circuit 42 in gate strip 18. The output of AND circuit 42, which signies a count of seven pulses and which is therefore the complementary count of two, is provided on conductor 19 to one of the fixed contacts of selector switch 24. As previously described, the outputs of stages l, 2, 4 and 8 of counter 22 are provided `to converter 25 which includes a gate strip 43. Gate strip 43 includes four two-input AND gates and is similar to gate strip 18 in that it is advantageously an integrated circuit strip. The 1 out' from counter 22 is connected to one input of each of AND gates 44, 46 and 47 in gate strip 43. The 2 output from counter 22 is connected to one input of each of gates 44 and 45. The 4 output is connected to the other input of gate 45 and the other input of gate 416. The 8 output is connected to the remaining input of gate 47. Outputs 1, 2, 4 and 8 are also connected directly to appropriate fixed contacts on selector switch 24. The 2 and 8 outputs are also connected to the two inputs of an AND gate 48 which provides the reset and carry pulse on conductor 20.

The connections of AND gates 44-48 are made in accordance with the truth table shown in FIG. 5. The binary outputs 1, 2, 4 and 8 for each ofdecimal counts -10 are shown in the table. lReferring to decimal count 1 in FIG. 5, it will be seen that the only output is the 1 output. This is therefore a count of l or a complement count of 8. This is shown directly in the tabulation of FIG. 6 in which the left-hand column shows the actual count, the center column shows vthe binary elements of counter 22 which produce an output at that count, and the third column shows the complementary count equivalent to the direct count and denoted by outputs from the binary elements listed. In FIG. 4 this combination is accomplished by the connections of the AND circuits as shown. For example, AND gate 45 combines the outputs of elements 2 and 4 to produce an output when the count reaches 6 which is equivalent to a complement count of 3. The output of gate 45 is therefore connected to the sixth position on the selector switch 24.

Selector switch 24, as seen in FIG. 4, is shown with two arrays of numbers, one outside of the stationary contacts of the selector switch and the other inside. The outside array of numbers shows the actual pulse count whereas the inside array (the numbers within the boxes) shows the complement count. In apparatus including selector switch 24, the knob on the face of the instrument includes a pointer capable of being set to any one of the ten positions of the switch. Those positions are identified by the numbers shown in the inside array of numbers on FIG. 4. Thus, if the desired interval for the timer is to be, for example, 3 in the tens digit, the knob of switch 24 would be set at 3. This setting would move the movable contact of selector switch 24 to the position shown in FIG. 4. Gate 11 would then be activated as previously described to allow pulses to emanate from pulse source 10 (FIG. 3) and be delivered to the timer and to counter 22. When counter 22 has accumulated six pulses, indicating that the interval timer has also accumulated six pulses, a signal would be provided to gate 21.

In the aforementioned example where it is desired to achieve a timer interval of 547 hours it was mentioned that the presetter should supply 1,000-547:453 pulses. If the hundreds, tens and units portions (assuming a 1,000 hour presetter) were each the same as that shown in FIG. 4, only 452 pulses would be delivered. In other words, if the operator were to set the knobs of the switches 32, 24 and 17 to the indicated positions 5, 4 and 7 respectively, the pulse source would be turned olf when the complements 4, 5 and 2, respectively appeared. To obtain the one additional pulse the indicia associated with units switch 17 is shifted one position. As a result, a 7 setting of the units switch would produce a signal on the wiper of switch 17 on a complementary count of 3 and, hence, the pulse source would be turned off after the 453rd pulse. An alternative approach would be to construct the reset circuits for counters 15, 22, `30 and 35 so that when push-button switch i8 (FIG. 2A) is actuated the counters are reset to 9999 instead of 0000 to thereby automatically add one additional pulse.

A modified embodiment of apparatus capable of performing the same presetting operation is shown in FIG. 7, In FIG. 7 an oscillator or pulse source 50 provides pulses to one input of an AND gate 51, the other input of which is supplied from the output of a bistable circuit 52. As in FIG. 3, bistable circuit 52 is placed in its set state by momentarily closing a normally open switch 53. Bistable circuit 52 is reset, or placed in its oit state, by a signal on conductor 54 from an AND gate 55. Also in a manner similar to FIG. 3, AND gate 55 is a four input AND gate, the inputs to which are connected to the movable contacts of four selector switches S6, 57, 58 and 59.

The major difference between the apparatus of FIG. 7 and the apparatus of FIG. 3 lies in the nature of the counter and logic circuit arrangement. In FIG. 7, rather than using binary counters, the apparatus uses a serially connected group of ring counters or shift registers, the units register 60 being a combination of two tive-bit shift registers 61 and 62 which are now commercially available in integrated circuit form. The input to register 60 is provided from the output of AND gate 51 and is connected to the low bit stage of register 61, the output of that stage being connected directly to the lowest bit of the second register 62. The output of the register 62 is connected to the tens counters and is also connected as a feedback reset signal to the input of register 61. The tens,

hundreds and thousands registers, identified as 63, 64 and 65, are similarly connected. Each stage of the units register is connected to one contact of selector switch 56, the zero level being connected to the nine contact to provide complementary outputs as previously described. The operation of the unit is substantially the same as that described in FIG. 3 and need not be repeated here.

FIG. 8 is a schematic illustration of a pulse source along with associated turn on and turn off circuits. The arrangement shown in FIG. 8 is an alternative for the flip-flop circuit and AND circuit combination as shown in FIGS. 3 and 7, FIG. 8 corresponding to block diagram FIG. 2A.

Pulse source 100 is a free-running multivibrator circuit including two NPN type transistors 101 and 102. The collectors of the transistors are connected to the positive source via resistors 104 and 103, respectively, whereas the bases thereof are coupled to the positive source via resistors 105 and 106. The cross-coupling is provided by capacitors 107 and 108, capacitor 107 being coupled between the collector of transistor 102 and the base of transistor 101 and capacitor 108 being coupled between the collector of transistor 101 and the base of transistor 102. The base of transistor 102 is coupled to the anode of a diode 109 and the cathode of the diode is connected to ground.

If the emitters of transistors 101 and 102 are coupled to ground the multivibrator circuit operates in conventional fashion with the transistors 101 and 102 becoming alternately conductive to provide a square wave output signal at the collector of transistor 101. The frequency is determined primarily by capacitors 107 and 108. The output appearing at the collector of transistor 101 is passed through suitable amplifier circuits 111 and 112 which go respectively to the timer circuit (as shown in FIG. 2B) and to the counter circuits within the presetter unit.

The turn-on circuit for pulse source 100 is coupled to the emitter of transistor 101. Turn-on circuit 120 includes a silicon controlled rectifier 121 having its anode coupled to the emitter of transistor 101 and its cathode connected to ground. An input terminal for the turn-on circuit as coupled to the gate element of SCR 121 via a resistor 123, the gate element also being coupled to ground via a resistor 124. A supply of anode current is provided by a resistor 122 coupled between the anode of SCR 121 and the positive source.

The turn-on circuit eliminates problems associated with switch bounce as may occur when switch (FIG. 2A)

is placed in the preset position to initiate the presetter operation. If contact is made momentarily there would be a tendency for the presetter circuits to initiate operation and then falter. By using SCR 121 the initial contact of the switch applies a potential to the gate of SCR 121 via resistor 123 which renders the SCR conductive to, in turn, turn on pulse source 100. The SCR has a latching characteristic so that once rendered conductive it remains conductive and, therefore, problems associated with switch bounce are eliminated.

The turn-olf circuit 130 is coupled to the emitter of the other transistor 102 of pulse source 100. The turnol circuit includes an NPN type transistor 131 having its collector coupled to the emitter of transistor 102 via a diode 132. The emitter of transistor 131 is connected directly to ground. The base of transistor 131 as coupled to an input terminal via an input resistor 134, and the base is also coupled to ground through a base resistor 133.

The logic circuitry associated with the pulse source 100 is such that a positive signal is normally applied at the base of transistor 131 and, therefore, transistor 131 is normally conductive. Accordingly, when turn-on circuit 120 is activated to render SCR 121 conductive, the emitters of both of transistors 101 and 102 are coupled to ground and, therefore, the pulse source begins to operate. Subsequently, if the signal applied to the base of transistor 131 drops to ground, as it would do in a turnoff situation, transistor 131 becomes non-conductive. Accordingly, the ground connection for transistor 102 of the pulse source is removed and, therefore, the pulse source ceases operation.

The indicator control circuit (indicator 7 in FIG. 2A) is illustrated in FIG. 9. The function of this circuit is to detect when the operator has properly rst activated the reset circuitry and, thereafter, has maintained the unit in the preset position sufficiently for a proper preset.

An SCR 150 is utilized to condition the indicating circuit 4whenever the operator has actuated reset push button 8 while switch 5 is in the reset position. As noted in FIG. 2A a potential is applied to indicator unit 7 under these circumstances.

The anode of SCR 150 is coupled to the positive source via a resistor 142, the cathode being connected to ground. The gate element is coupled to an input terminal via an input resistor 151 and is also coupled to ground via a resistor 152. Accordingly, when a positive potential is applied to the gate of SCR 150 via resistor 151 the SCR becomes conductive and current flows through resistor 142 and the SCR. Since the SCR is conductive the potential at the anode thereof is very close to ground. When SCR 150 is conductive the indicator circuit 7 is considered as being conditioned The output indication is provided by a lamp bulb 140 which is connected in series with a resistor 141 between the collector of an NPN type transistor 136 and the positive source. Another NPN transistor is used as a pre-amplifier, this transistor having its collector coupled to the positive source via a resistor 137 and its emitter connected to ground. The base of transistor 135 is coupled to an input terminal via an input resistor 138 and the base is also coupled to ground via a base resistor 139. The collector of transistor 135 is connected directly to the base of transistor 136.

Normally, a positive potential is applied to the base of transistor 135 which maintains this transistor conductive. The potential at its collector therefore is close to ground which, in turn, maintains transistor 136 in a non-conductive state. Light bulb 140 is therefore not illuminated. However, if the potential applied to the base of transistor 135 falls to zero, this being the same condition which is applied to turn-off circuit 130, transistor 135 becomes non-conductive and, therefore, its collector Ipotential tends to rise. This drives the base of transistor 136 positive and, therefore, transistor 136 can become conductive. If SCR is conductive, current ows through the collector-emitter circuit of transistor 136 to thereby energize light bulb 140.

It should be noted, that light bulb 140 can be energized only if SCR 150 is first rendered conductive by proper operation of the reset circuitry, and if the potential at the base of transistor 135 subsequently falls to zero to thereby render transistor 136 conductive. Accordingly, when the indicator circuit is connected as shown in FIG. 2A illumination of light bulb 140 will indicate to the operator that both the reset operation and the preset operation have been properly carried out.

While certain advantageous embodiments have been chosen to illustrate the invention, it will be understood by those skilled in the art that various changes and modifications can be made therein without departing from the scope of the invention as defined in the appended claims.

What is claimed is:

1. In a preset timer system, the combination of a timer for producing an actuation after a preselected interval including:

a timer pulse generator for producing pulses at a real time rate, and

a timer count connected to said timer pulse generating means and operative to count said pulses in real time, said timer counter means being further operative to produce an actuation when a full count is achieved; and a presetter for said timer including:

selector switch means bearing indicia corresponding to desired real time intervals for said timer,

a presetter pulse generator for producing pulses at a compressed non-real time rate,

first circuit means for coupling said presetter pulse generator to apply said compressed non-real time pulses to said timer counter While being preset, an electronic presetter counter, and

second circuit means so interconnecting said selector switch means and said presetter counter that said presetter counter counts said compressed non-real time pulses and limits the number of pulses supplied to said timer counter to a number which is the complement of the desired real time interval then indicated on the indicia of said selector switches.

2. The system according to claim 1 wherein said presetter further includes a reset circuit connected to reset said timer counter and said presetter counter prior to the application of said compressed non-real time pulses to said timer counter.

3. The system according to claim 2 further including an indicating circuit, said indicating circuit being:

coupled to said reset circuit and condition for operation in response to activation of said reset circuit, and

coupled to said second circuit means to provide a visible indication t the operator after said compressed non-real. time pulses have been applied if said indication circuit had previously been conditioned by activation of said reset circuit.

4. The system according to claim 1 wherein said presetter pulse generator is continuously operable and wherein said second circuit means comprises gate means at the output of said presetter pulse generator.

5. The system according to claim 1 wherein said second circuit means comprises a turn-efrr circuit connected to control operation of said presetter pulse generator.

6. The -system according to claim l1 further comprising:

switch means for initiating said preset operation, and

turn-on circuit means connected to said switch means and said presetter pulse generator to initiate operation of said presetter pulse generator in response to activation of said switch means.

7. The system according to claim 6 wherein said turnon circuit has a latching characteristic and remains on in response to the first actuation of said switch means thereby eliminating contact bounce problems.

8. A presetter for a timer operative to count real time impulses and provide an actuation upon reaching a full count, the combination of a source of electrical impulses at a compressed non-real time rate;

a plurality of decimal counters connected in cascade to count said electrical impulses;

selectively operable circuit means coupled to said source of electrical impulses and said decimal counters, said circuit means being operable to permit passage of electrical pulses to said decimal counters and said timer when activated;

a plurality of selector switches each including:

a movable contact,

a decimal indicia disposed for view by the operator to indicate the decimal position of said movable contact, and

a plurality of stationary contacts;

circuit means for connecting the outputs of each decimal counter to the stationary contacts of a different one of said selector switches, said connections being in a reverse sequence so that the decimal counter output coupled to the movable contact corresponds to the complement of the then indicated decimal indicia;

AND circuit means, each of said movable contacts `being connected to a different input of said AND circuit means and said AND circuit means being connected to said selectively operable circuit means to deactivate the same when an input signal is simultaneously received from all of said movable contacts.

9. A presetter according to claim 8 wherein each of said decimal counters includes:

four cascade binary stages; and

binary-to-decimal decoding logic circuits responsive to the output of said binary stages and operative to provide decimal output indications.

10. An apparatus for delivering a preselected number of electrical impulses to a utilization device, comprising the combination of a source of electrical impulses;

a gate circuit having one input connected to said source of impulses;

a bistable circuit having an output connected to another input of said gate circuit;

means for placing said bistable circuit in an ON condition to provide said gate circuit with an activating signal to permit pulses to pass to the utilization device;

a plurality of decimal counter means connected serially for accumulating impulses from said gate circuit and for providing output signals at each count;

irst circuit means for providing the output of said gate circuit to the input of one of said binary counters; plurality of selector switches each having multiple fixed contacts in a decimal sequence, and a movable contact, said fixed contacts of each switch being connected to the outputs of said decimal counter means in reverse sequence; AND circuit means having a number of inputs equal to the number of selector switches, and an output;

second circuit means for interconnecting said movable contacts of said selector switches and said inputs of said AND circuit means; and

third circuit means for connecting the output of said AND circuit means to said bistable circuit to place said bistable circuit in an OFF condition.

11. An apparatus according to claim 10 wherein each of said plurality of decimal counter means comprises:

a binary counter having 1, 2, 4 and 8 count outputs;

and

logic circuit means for combining said l, 2, 4 and 8 outputs to provide a decimal complementary count.

12. Apparatus according to claim 10 wherein each of said plurality of decimal counter means comprises:

a ten stage ring counter having the first stage connected to receive input count signals; and

feedback means to provide a carry pulse from the tenth stage to the iirst stage;

said plurality of counter means being connected serially to provide sections in increasing powers of l0.

References Cited UNITED STATES PATENTS 2,493,627 l/ 1950 Grosdoif S28-48X 2,519,184 8/1950 GrOSdOff 328-48 3,096,483 7/ 1963 Ransom 328-48 3,241,017 3/ 1966 Madsen et al 307--271X DONALD D. FORRER, Primary Examiner R. C. WOODBRIDGE, Assistant Examiner U.S. Cl. X.R. 

